1. Field of the Invention
The present invention relates to an IC test equipment to test semiconductor integrated circuits, specifically to an IC test equipment that has a common judgment circuit and measures a plurality of devices under test in parallel, a measurement method in the IC test equipment, and a storage medium of the same.
2. Description of the Related Art
In recent years, circuits used in various electronic equipments have been made into ICs (Integrated Circuits) with impetus. IC or LSI (Large Scale Integrated circuit) is embodied by printing, vapor deposition, and other methods, by which the functions of resistors, capacitors, transistors, and other devices are formed. However, there are some dispersions in characteristics among these products which are mass-produced. The IC test equipment is to test whether the characteristic of the IC or LSI with such dispersions meets the specification or not.
When semiconductor integrated circuits such as an IC are tested using an IC test equipment, it is effective that a plurality of devices under test (Device Under Test: DUT) are tested in parallel by one and the same device program.
A conventional IC test equipment 11 will now be described with reference to FIG. 2, by which a plurality of devices under test can be tested in parallel.
FIG. 2 is a block diagram to illustrate the circuit configuration of the conventional IC test equipment 11, in which devices under test (1) through (5) are mounted on an IC measurement board 30.
In FIG. 2, the IC test equipment 11 comprises a pattern generator 12, controller 13, clock generator 14, judgment circuit 15, register circuit 16, data generating circuit 17, and clock generator 20, and tests a plurality of devices under test (1) through (5) mounted on the IC measurement board 30.
First, the controller 13 outputs to the clock generator 14 a control signal that indicates the very device under test a plurality of the foregoing devices under test (1) through (5), and controls the clock generator 14 to output the Enable signal to arbitrary device to be tested. The clock generator 14 generates the Enable signal for bringing the devices under test into the Enable state, and supplies the Enable signal only to the arbitrary device to be tested out of a plurality of the devices under test on the basis of the control signal inputted from the controller 13.
Next, the pattern generator 12 generates a pattern signal required for testing the devices under test, and outputs the pattern signal to each of the foregoing devices under test (1) through (5). On the other hand, the data generating circuit 17 outputs to the clock generator 20 a timing data T1 for the clock signal (strobe signal to define the time-position when good or not good is judged) generated by the clock generator 20.
And, the judgment circuit 15 judges the voltage level of a signal when an output terminal of a plurality of the foregoing devices under test is short-circuited, and transfers the result to the register circuit 16. In practice, the clock generator 14 controlled by the controller 13 selects one arbitrary device under test out of a plurality of the devices under test, and brings only the selected device under test into the Enable state. And, the judgment circuit 15 judges the voltage level of the signal outputted from the output terminal of the selected device under test, and transfers it as a voltage level data to the register circuit 16.
And, the clock generator 20 generates the strobe signal on the basis of the timing data T1 inputted from the data generating circuit 17 to output to the register circuit 16, and controls to latch inside the register circuit 16 the voltage level data inputted to the register circuit 16 from the judgment circuit 15 when the strobe signal is generated. The register circuit 16 latches to hold inside thereof the voltage level data inputted from the judgment circuit 15, on the basis of the timing of the strobe signal inputted from the clock generator 20.
However, in the foregoing IC test equipment 11, the time from when the pattern signal is outputted from the pattern generator 12 until when the pattern signal propagates through a device under test, passes through the judgment circuit 15, and reaches the register circuit 16 differs depending on the path corresponding to the device under test that the pattern signal propagates through. T1n is the time from when the pattern signal is outputted until when the pattern signal propagating through the n-th device under test (n: anyone of the numbers (1) through (5) of the devices under test) reaches the register circuit 16. T11, T12, . . , T15 are the times, based on the above definition, when the pattern signal passes through the devices under test (1), (2), . . . , (5), respectively, which have different values each other. T1 is defined as the average value of the times T11, T12, . . , T15.
Naturally, the T1 as the average of the times T11, T12, . . , T15 is deviated from the times T11, T12, . . , T15 by each of the paths. The clock generator 20 generates the strobe signal on the basis of the timing data T1 that contains the above deviations or errors from the times T11, T12, . . , T15 by each of the paths corresponding to a plurality of the devices under test. Therefore, it is unavoidable that the voltage level data inputted from the judgment circuit 15, which is latched by the register circuit 16 and held inside thereof on the basis of the timing of the strobe signal, involves measurement deviations between the devices under test.